Signal Assignments

Signal Assignments

Signals are declared outside the process using the following statement:

signal list_of_signal_names: type [ := initial value] ;

signal SUM, CARRY: std_logic;

signal CLOCK: bit;

signal TRIGGER: integer :=0;

signal DATA_BUS: bit_vector (0 to 7);

signal VALUE: integer range 0 to 100;

Signals are updated when their signal assignment statement is executed, after a certain delay, as illustrated below,

SUM <= (A xor B) after 2 ns;

If no delay is specified, the signal will be updated after a delta delay. One can also specify multiple waveforms using multiple events as illustrated below,

signal wavefrm : std_logic;

wavefrm <= ‘0’, ‘1’ after 5ns, ‘0’ after 10ns, ‘1’ after 20 ns;

It is important to understand the difference between variables and signals, particularly how it relates to when their value changes. A variable changes instantaneously when the variable assignment is executed. On the other hand, a signal changes a delay after the assignment expression is evaluated. If no delay is specified, the signal will change after a delta delay. This has important consequences for the updated values of variables and signals.

Example of a process using Signals

architecture SIGN of EXAMPLE is

signal TRIGGER, RESULT: integer := 0;

signal signal1: integer :=1;

signal signal2: integer :=2;

signal signal3: integer :=3;

begin

process

begin

wait on TRIGGER;

signal1 <= signal2;

signal2 <= signal1 + signal3;

signal3 <= signal2;

RESULT <= signal1 + signal2 + signal3;

end process;

end SIGN;

Example of a process using Variables

architecture VAR of EXAMPLE is

signal TRIGGER, RESULT: integer := 0;

begin

process

variable variable1: integer :=1;

variable variable2: integer :=2;

variable variable3: integer :=3;

begin

wait on TRIGGER;

variable1 := variable2;

variable2 := variable1 + variable3;

variable3 := variable2;

RESULT <= variable1 + variable2 + variable3;

end process;

end VAR