Describing a design

Describing a design:

In VHDL an entity is used to describe a hardware module.

An entity can be described using,
1. Entity declaration.
2. Architecture.
3. Configuration
4. Package declaration.
5. Package body.

Entity declaration:
It defines the names, input output signals and modes of a hardware module.

Syntax:
entity entity_name is
Port declaration;
end entity_name;

An entity declaration should starts with ‘entity’ and ends with ‘end’ keywords.

Ports are interfaces through which an entity can communicate with its environment. Each port must have a name, direction and a type. An entity may have no port declaration also. The direction will be input, output or inout.

In	Port can be read
Out	Port can be written
Inout	Port can be read and written
Buffer	Port can be read and written, it can have only one source.

Architecture:

It describes the internal description of design or it tells what is there inside design. Each entity has atleast one architecture and an entity can have many architecture. Architecture can be described using structural, dataflow, behavioral or mixed style. Architecture can be used to describe a design at different levels of abstraction like gate level, register transfer level (RTL) or behavior level.

Syntax:
architecture architecture_name of entity_name
architecture_declarative_part;
begin
Statements;
end architecture_name;

Here we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the begin and end keyword. Architecture declarative part may contain variables, constants, or component declaration.

Configuration:

If an entity contains many architectures and any one of the possible architecture binding with its entity is done using configuration. It is used to bind the architecture body to its entity and a component with an entity.

Syntax:
configuration configuration_name of entity_name is
block_configuration;
end configuration_name.

Block_configuration defines the binding of components in a block. This can be written as
for block_name
component_binding;
end for;
block_name is the name of the architecture body. Component binding binds the components of the block to entities. This can be written as,
for component_labels:component_name
block_configuration;
end for;

Package declaration:

Package declaration is used to declare components, types, constants, functions and so on.

Syntax:
package package_name is
Declarations;
end package_name;

Package body:

A package body is used to declare the definitions and procedures that are declared in corresponding package. Values can be assigned to constants declared in package in package body.

Syntax:
package body package_name is
Function_procedure definitions;
end package_name;

The internal working of an entity can be defined using different modeling styles inside architecture body. They are
1. Dataflow modeling.
2. Behavioral modeling.
3. Structural modeling.

Structure of an entity: