HISTORY OF VERILOG

HISTORY OF VERILOG

Verilog was started in the year 1984 by Gateway Design Automation Inc as a proprietary hardware modeling language. It is rumored that the original language was designed by taking features from the most popular HDL language of the time, called HiLo, as well as from traditional computer languages such as C. At that time, Verilog was not standardized and the language modified itself in almost all the revisions that came out within 1984 to 1990.

Verilog simulator first used in 1985 and extended substantially through 1987. The implementation of Verilog simulator sold by Gateway. The first major extension of Verilog is Verilog-XL, which added a few features and implemented the infamous "XL algorithm" which is a very efficient method for doing gate-level simulation.

Later 1990, Cadence Design System, whose primary product at that time included thin film process simulator, decided to acquire Gateway Automation System, along with other Gateway products., Cadence now become the owner of the Verilog language, and continued to market Verilog as both a language and a simulator. At the same time, Synopsys was marketing the top-down design methodology, using Verilog. This was a powerful combination.

In 1990, Cadence organized the Open Verilog International (OVI), and in 1991 gave it the documentation for the Verilog Hardware Description Language. This was the event which "opened" the language.

BASIC CONCEPTS

Hardware Description Language

Two things distinguish an HDL from a linear language like “C”:

Concurrency:

• The ability to do several things simultaneously i.e. different code-blocks can run concurrently.

Timing:

• Ability to represent the passing of time and sequence events accordingly

VERILOG Introduction

• Verilog HDL is a Hardware Description Language (HDL).

• A Hardware Description Language is a language used to describe a digital system; one may describe a digital system at several levels.

• An HDL might describe the layout of the wires, resistors and transistors on an Integrated Circuit (IC) chip, i.e., the switch level.

• It might describe the logical gates and flip flops in a digital system, i.e., the gate level.

• An even higher level describes the registers and the transfers of vectors of information between registers. This is called the Register Transfer Level (RTL).

• Verilog supports all of these levels.

• A powerful feature of the Verilog HDL is that you can use the same language for describing, testing and debugging your system.

VERILOG Features

• Strong Background:-Supported by OVI, and standardized in 1995 as IEEE std 1364.

• Industrial support:-Fast simulation and effective synthesis (85% were used in ASIC foundries by EE TIMES)

• Universal :-Allows entire process in one design environment (including analysis and verification)

• Extensibility :-Verilog PLI that allows for extension of Verilog capabilities