Levels of Abstraction

Abstraction

Abstraction is defined as the hiding of information that is too detailed. It is therefore necessary to differentiate between essential and non-essential information. Information that is not important for the current view of the problem will be left out from the description. Abstraction levels are characterized by the kind of information that is common to all models of this level.

A model is said to be of a certain abstraction level if every module has the same degree of abstraction. If this is not the case than the model will be a mixture of different abstraction levels.

Abstraction Levels in IC Design

The four abstraction levels of a digital circuit design are shown in the figure. The functional description of the model is outlined in the behavioural level. There is no system clock and signal transitions are asynchronous with respect to the switching time. Usually, such descriptions are simulatable, only, but not synthesizable.

In the next step, the design is divided into combinational logic and storage elements. This is called the Register Transfer Level (RTL). The storage elements (Flip Flops (FFs), latches) are controlled by a system clock. In synchronous designs, FFs should be used (driven by the edge of the clock signal) exclusively, because transparent latches (driven by the level of a control signal) are not spike-proof. For the description on RT level only 10 to 20 percent of all VHDL language constructs are needed and a strict methodology has to be followed. This description on RT level is called synthesizable description.

On the logic level, the design is represented as a netlist with logic gates (AND, OR, NOT, ...) and storage elements. The final layout is at the bottom of the hierarchy. The different cells of the target technology are placed on the chip and the connections are routed. After the layout has been verified, the circuit is ready for the production process.

Abstraction levels and VHDL

VHDL is applicable to the upper three abstraction levels. It is not suitable to describe a layout. The design entry in behavioural and RT level is usually done by text editors. Graphical tools are also available but experienced users often find it easier to write the code by hand. On the gate level, a schematic is modified as VHDL netlist descriptions tend to become too complex pretty soon.

The transition from an upper abstraction level to a lower one is supported more or less efficiently by software.

Logic synthesis, however, has been perfected in recent years. As long as the designer confines himself to certain simple VHDL constructs that are sufficient for RT level descriptions, the synthetis tools will be able to reproduce the behaviour in the logic level.

As a result of the ongoing research in efficient place and route algorithms the step from the logic level to the final layout has been widely automated for digital standard cell designs.

Description of Abstraction Levels

In the behaviour level, complete systems can be modelled. Bus systems or complex algorithms are described without considering synthesizability. The stimuli for simulation of RTL models are described in the behaviour level, for example. Stimuli are signal values of the input ports of the model and are described in the testbench, sometimes called validation bench.

The designer has to take great care to find a consistent set of input stimuli that do not contradict the specification. The responses of the model have to be compared with the expected values which, in the simplest case, can be done with the help of a waveform diagram that shows the simulated signal values.

On the RT level, the system is described in terms of registers and logic that calculates the next value of the storage elements. It is possible to split the code into two blocks (cf. process statement) that contain either purely combinational logic or registers. The registers are connected to the clock signal and provide for synchronous behaviour. In practice, the strict separation of Flip Flops from combinational logic is often annulated and clocked processes describe the registers and the corresponding update functions.

The gate netlist is generated from the RT description with the help of a synthesis tool. For this task, a cell library for the target technology which holds the information about all available gates and their parameters (fan-in, fan-out, delay) is needed.

Based upon this gate netlist the circuit layout is generated. The resulting wire lengths can be converted into propagation delays which can be fed back into the gate level model (back annotation). This allows for thorough timing simulations without the need for additional simulator software.