Data Flow Modeling

DATA FLOW MODELING

For small circuits, the gate-level modeling approach works very well because the number of gates is limited and the designer can instantiate and connects every gate individually. Also, gate-level modeling is very intuitive to a designer with a basic knowledge of digital logic design. However, in complex designs the number of gates is very large. Thus, designers can design more effectively if they concentrate on implementing the function at a level of abstraction higher than gate level. Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than instantiation of individual gates.

Dataflow modeling has become a popular design approach as logic synthesis tools have become sophisticated. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow. For maximum flexibility in the design process, designers typically use a Verilog description style that combines the concepts of gate-level, dataflow, and behavioral design. In the digital design community, the term RTL (Register Transfer Level) design is commonly used for a combination of dataflow modeling and behavioral modeling.

Continuous Assignment Statements

A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net. A continuous assignment replaces gates in the description of the circuit and describes the circuit at a higher level abstraction. A continuous assignment statement starts with the keyword assign. They represent structural connections.

• They are used for modeling Tri-State buffers.
• They can be used for modeling combinational logic.
• They are outside the procedural blocks (always and initial blocks).
• The continuous assign overrides any procedural assignments.
• The left-hand side of a continuous assignment must be net data type.

Syntax: assign (strength, strength) #(delay) net = expression;

Example - One bit Adder design using continuous assignment statement

module adder_using_assign ();

reg a, b;

wire sum, carry;

assign #5 {carry,sum} = a+b;

initial begin

$monitor (" A = %b B = %b CARRY = %b SUM = %b",a,b,carry,sum);

#10 a = 0;

b = 0;

#10 a = 1;

#10 b = 1;

#10 a = 0;

#10 b = 0;

#10 $finish;

end

endmodule

Example - Tri-state buffer using continuous assignment statement

module tri_buf_using_assign();

reg data_in, enable;

wire pad;

assign pad = (enable) ? data_in : 1'bz;

initial begin

  $monitor ("TIME = %g ENABLE = %b DATA : %b PAD %b", 

    $time, enable, data_in, pad);

  #1 enable = 0;

  #1 data_in = 1;

  #1 enable = 1;

  #1 data_in = 0;

  #1 enable = 0;

  #1 $finish;

end

endmodule

Propagation Delay

Continuous Assignments may have a delay specified; only one delay for all transitions may be specified. A minimum: typical: maximum delay range may be specified.

Example - Tri-state buffer

module tri_buf_using_assign_delays();

reg data_in, enable;

wire pad;

assign #(1:2:3) pad = (enable) ? data_in : 1'bz;

initial begin

  $monitor ("ENABLE = %b DATA : %b PAD %b",enable, data_in,pad);

  #10 enable = 0;

  #10 data_in = 1;

  #10 enable = 1;

  #10 data_in = 0;

  #10 enable = 0;

  #10 $finish;

end

endmodule