Data Flow Modeling

DATA FLOW MODELING

For small circuits, the gate-level modeling approach works very well because the number of gates is limited and the designer can instantiate and connects every gate individually. Also, gate-level modeling is very intuitive to a designer with a basic knowledge of digital logic design. However, in complex designs the number of gates is very large. Thus, designers can design more effectively if they concentrate on implementing the function at a level of abstraction higher than gate level. Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than instantiation of individual gates.

Dataflow modeling has become a popular design approach as logic synthesis tools have become sophisticated. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow. For maximum flexibility in the design process, designers typically use a Verilog description style that combines the concepts of gate-level, dataflow, and behavioral design. In the digital design community, the term RTL (Register Transfer Level) design is commonly used for a combination of dataflow modeling and behavioral modeling.

Continuous Assignment Statements

A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net. A continuous assignment replaces gates in the description of the circuit and describes the circuit at a higher level abstraction. A continuous assignment statement starts with the keyword assign. They represent structural connections.

• They are used for modeling Tri-State buffers.
• They can be used for modeling combinational logic.
• They are outside the procedural blocks (always and initial blocks).
• The continuous assign overrides any procedural assignments.
• The left-hand side of a continuous assignment must be net data type.

Syntax: assign (strength, strength) #(delay) net = expression;

Example - One bit Adder design using continuous assignment statement

module adder_using_assign ();

reg a, b;

wire sum, carry;

assign #5 {carry,sum} = a+b;

initial begin

$monitor (" A = %b B = %b CARRY = %b SUM = %b",a,b,carry,sum);

#10 a = 0;

b = 0;

#10 a = 1;

#10 b = 1;

#10 a = 0;

#10 b = 0;

#10 $finish;

end

endmodule

Example - Tri-state buffer using continuous assignment statement

module tri_buf_using_assign();

reg data_in, enable;

wire pad;

assign pad = (enable) ? data_in : 1'bz;

initial begin

  $monitor ("TIME = %g ENABLE = %b DATA : %b PAD %b", 

    $time, enable, data_in, pad);

  #1 enable = 0;

  #1 data_in = 1;

  #1 enable = 1;

  #1 data_in = 0;

  #1 enable = 0;

  #1 $finish;

end

endmodule

Propagation Delay

Continuous Assignments may have a delay specified; only one delay for all transitions may be specified. A minimum: typical: maximum delay range may be specified.

Example - Tri-state buffer

module tri_buf_using_assign_delays();

reg data_in, enable;

wire pad;

assign #(1:2:3) pad = (enable) ? data_in : 1'bz;

initial begin

  $monitor ("ENABLE = %b DATA : %b PAD %b",enable, data_in,pad);

  #10 enable = 0;

  #10 data_in = 1;

  #10 enable = 1;

  #10 data_in = 0;

  #10 enable = 0;

  #10 $finish;

end

endmodule

Behavioral Modeling

BEHAVIORAL MODELING

Verilog provides designers the ability to describe design functionality in an algorithmic manner. In other words, the designer describes the behavior of the circuit. Thus, behavioral modeling represents the circuit at a very high level of abstraction. Design at this level resembles C programming more than it resembles digital circuit design. Behavioral Verilog constructs are similar to C language constructs in many ways. Verilog is rich in behavioral constructs that provide the designer with a great amount of flexibility.

Procedural Blocks

Verilog behavioral code is inside procedure blocks, but there is an exception: some behavioral code also exist outside procedure blocks. We can see this in detail as we make progress.

There are two types of procedural blocks in Verilog:

• initial: initial blocks execute only once at time zero (start execution at time zero).
• always: always blocks loop to execute over and over again; in other words, as the name suggests, it executes always.

Example – initial

module initial_example();

reg clk,reset,enable,data;

initial begin

 clk = 0;

 reset = 0;

 enable = 0;

 data = 0;

end

endmodule

In the above example, the initial block execution and always block execution starts at time 0. Always block waits for the event, here positive edge of clock, whereas initial block just executed all the statements within begin and end statement, without waiting.

Example – always

module always_example();

reg clk,reset,enable,q_in,data;

always @ (posedge clk)

if (reset)  begin

   data <= 0;

end else if (enable) begin   

   data <= q_in;

end

endmodule

In an always block, when the trigger event occurs, the code inside begin and end is executed; then once again the always block waits for next event triggering. This process of waiting and executing on event is repeated till simulation stops.

Procedural Assignment Statements

Procedural assignment statements assign values to reg, integer, real, or time variables and cannot assign values to nets (wire data types)

• You can assign to a register (reg data type) the value of a net (wire), constant, another register, or a specific value.

Example - Bad procedural assignment

module initial_bad();

reg clk,reset;

wire enable,data;

initial begin

 clk = 0;

 reset = 0;

 enable = 0;

 data = 0;

end

endmodule

Example - Good procedural assignment

module initial_bad();

reg clk,reset;

wire enable,data;

initial begin

 clk = 0;

 reset = 0;

 enable = 0;

 data = 0;

end

endmodule

Procedural Assignment Groups

If a procedure block contains more than one statement, those statements must be enclosed within

• Sequential begin - end block
• Parallel fork - join block
  

When using begin-end, we can give name to that group. This is called named blocks.

Example - "begin-end"

module initial_begin_end();

reg clk,reset,enable,data;

initial begin

$monitor(

"%g clk=%b reset=%b enable=%b data=%b",

$time, clk, reset, enable, data);

#1 clk = 0;

#10 reset = 0;

#5 enable = 0;

#3 data = 0;

#1 $finish;

end

endmodule

Begin : clk gets 0 after 1 time unit, reset gets 0 after 11 time units, enable after 16 time units, data after 19 units. All the statements are executed sequentially.

Example - "fork-join"

module initial_fork_join();

reg clk,reset,enable,data;

initial begin

 $monitor("%g clk=%b reset=%b enable=%b data=%b", 

   $time, clk, reset, enable, data);

 fork

   #1  clk = 0;

   #10 reset = 0;

   #5  enable = 0;

   #3  data = 0;

 join

 #1 $display ("%g Terminating simulation", $time);

 $finish;

end

endmodule

Fork: clk gets its value after 1 time unit, reset after 10 time units, enable after 5 time units, data after 3 time units. All the statements are executed in parallel.

Sequential Statement Groups

The begin - end keywords:

• Group several statements together.
• Cause the statements to be evaluated sequentially (one at a time)
• -> Any timing within the sequential groups is relative to the previous statement.
• -> Delays in the sequence accumulate (each delay is added to the previous delay)
• -> Block finishes after the last statement in the block.

Example – sequential

module sequential();

reg a;

initial begin

  $monitor ("%g a = %b", $time, a);

  #10 a = 0;

  #11 a = 1;

  #12 a = 0;

  #13 a = 1;

  #14 $finish;

end

endmodule

Parallel Statement Groups

The fork - join keywords:

• Group several statements together.
• Cause the statements to be evaluated in parallel (all at the same time).
• -> Timing within parallel group is absolute to the beginning of the group.
• -> Block finishes after the last statement completes (Statement with highest delay, it can be the first statement in the block).\
  

Example – Parallel

module parallel();

reg a;

initial 

fork

  $monitor ("%g a = %b", $time, a);

  #10 a = 0;

  #11 a = 1;

  #12 a = 0;

  #13 a = 1;

  #14 $finish;

join

endmodule