Timing, Concurrency and Sequential Assignments

Timing

1. Transfer of values between components or within a component is done through wires and buses.

2. Transfer values: delays

3. VHDL need to model the timing property

Modelling Concept in VHDL

Process Concurrency

VHDL is designed to model the concept of concurrency. Basically, we can partition the system into several concurrent processes that would conceptually be running concurrently. Looking at the following example we can see the operation of concurrency.

entity ANDXOR is

port (

A, B: in bit;

C: in bit;

D: out bit);

end ANDXOR;

architecture ANDXOR_arch of ANDXOR is

signal T: bit;

begin

T <= A and B after 2 ns;

P0: process (T, C)

begin

D <= T xor C after 3 ns;

end process p0;

end AND_XOR;

The declared process present in one of the three states: running, active and suspended. A process is “running” when the simulator executing the process. A process is “active” when the process is waiting for the simulator to execute it. A process is “suspended” when it is not “running” or “active”. The below figure shows the basic process state transition diagram.

Fig:1 Process state transition

Concurrent and Sequential Statements

In VHDL, executable statements are categorized as concurrent statements and sequential statements. Concurrent statements are used model the concurrent behaviors. VHDL concurrent statements are block, process, generate, component instantiation, signal assignment, assert statements and procedure call statements. VHDL sequential statements are inherent from other high-level programming languages such as if, case, loop, signal assignment, variable assignment, return, exit and wait statements. Sequential statements are used to define algorithm for the execution of a subprogram like function and procedure or a process. They execute in the order in which they appear.

VHDL Concurrent Statements VHDL Sequential Statements

Block statement If statement

Process statement Case statement

Generate statement Loop statement

Procedure call statement Procedure call statement

Assert statement Assert statement

Signal assignment statement Signal assignment statement

Component instantiation statement Variable assignment statement

Exit statement

Wait statement

Return statement

Next statement

The important VHDL coding rules are as follows:

1.Only concurrent statements can be inside the architecture statement part.

2. Sequential statements can only appear inside the procedure and function body and inside the process statement.

3. Signals are used to communicate among the concurrent processes.

4. Local variables can only be declared inside the procedure, function and process statement. They are not visible outside of the procedure, function and process statement.