Modules and Ports

MODULES

A module in Verilog consists of distinct parts as shown in figure. A module definition always begins with the keyword module. The module name, port list, port declarations, and optional parameters must come first in a module definition. Port list and port declarations are present only if the module has any ports to interact with the external environment. The five components within a module are;

• variable declarations,
• dataflow statements
• instantiation of lower modules
• behavioral blocks
• tasks or functions.

These components can be in any order and at any place in the module definition. The endmodule statement must always come last in a module definition. All components except module, module name, and endmodule are optional and can be mixed and matched as per design needs. Verilog allows multiple modules to be defined in a single file. The modules can be defined in any order in the file.

Components of Verilog Module

Example Module Structure :

module ();

…..

….

Endmodule

Instances

A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name_, variables, parameters and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. In Example below, the top-level block creates four instances from the T-flip-flop (T_FF) template. Each T_FF instantiates a D_FF and an inverter gate. Each Instance must be given a unique name.

Example

// Define the top-level module called ripple carry

// counter. It instants 4 T-filpflops.

// four instances of the module T_FF are created. Each has a unique name.

// each instance is passed a set of signals

module ripple_carry_counter(q,clk,reset);

output [3:0]q;

input clk,reset;

T_FF tff0(q[0],clk,reset);

T_FF tff1(q[1],q[0],reset);

T_FF tff2(q[2],q[1],reset);

T_FF tff3(q[3],q[2],reset);

endmodule

// define the module T_FF. it instantiates a D-filpflop.

module T_FF(q,clk,reset);

output q;

input clk,reset;

wire d;

D_FF dff0(q,d,clk,reset);

not n1(d,q);

endmodule

PORTS

Ports provide the interface by which a module can communicate with its environment. For example, the input/output pins of an IC chip are its ports. The environment can interact with the module only through its ports. The internals of the module are not visible to the environment. This provides a very powerful flexibility to the designer. The internals of the module can be changed without affecting the environment as long as the interface is not modified. Ports are also referred to as terminals.

Port Declaration

All ports in the list of ports must be declared in the module. Ports can be declared as follows

Verilog Keyword Type of Port

input Input port

output Output port

inout Bidirectional port

Each port in the port list is defined as input, output, or inout, based on the direction of the port signal.

Port Connection Rules

One can visualize a port as consisting of two units, one unit that is internal to the module another that is external to the module. The internal and external units are connected. There are rules governing port connections when modules are instantiated within other modules. The Verilog simulator complains if any port connection rules are violated. These rules are summarized in below figure.

Port connection Rules

Inputs:

• Internally must be of net data type (e.g. wire)

• Externally the inputs may be connected to a reg or net data type

Outputs:

• Internally may be of net or reg data type

• Externally must be connected to a net data type

Inouts:

• Internally must be of net data type (tri recommended)

• Externally must be connected to a net data type (tri recommended)

Ports Connection to External Signals

There are two methods of making connections between signals specified in the module instantiation and ports in a module definition. The two methods cannot be mixed.

• Port by order list
• Port by name

Port by order list

Connecting port by order list is the most intuitive method for most beginners. The signals to be connected must appear in the module instantiation in the same order as the ports in the ports list in the module definition.

Syntax for instantiation with port order list:

module_name instance_name (signal, signal...);

From the below example, notice that the external signals a, b, out appear in exactly the same order as the ports a, b, out in the module defined in adder below.

Example

Port by name

For larger designs where the module have ,say 50 ports , remembering the order of the ports in the module definition is impractical and error prone. Verilog provided the capability to connect external signals to ports by the port names, rather than by position.

Syntax for instantiation with port name:

module_name instance_name (.port_name(signal), .port_name (signal)… );

From the below example, note that the port connections in any order as long as the port name in the module definition correctly matches the external signal.

Another advantage of connecting ports by name is that as long as the port name is not changed, the order of ports in the port list of a module can be rearranged without changing the port connections in the module instantiations.