Gate Level Modeling

GATE LEVEL MODELING

Verilog has built in primitives like gates, transmission gates, and switches. These are rarely used in design (RTL Coding), but are used in post synthesis world for modeling the ASIC/FPGA cells; these cells are then used for gate level simulation. Also the output netlist format from the synthesis tool, which is imported into the place and route tool, is also in Verilog gate level primitives.

Gate Types

A logic circuit can be designed by use of logic gates. Verilog supports logic gates as predefined primitives. Theses primitives are instantiated like modules except that they are predefined in Verilog and do not need a module definition. All circuit can be designed by using basic gates. There are two classes of basic gates: and/or gates and buf/not gates.

And/Or Gates

and/or gates have one scalar output and multiple scalar inputs. The first terminal in the list of gate terminals is an output and the other terminals are inputs. The output of a gate is evaluated as soon as one of the inputs changes. The and/or gates available in Verilog are shown below.

and or xor

nand nor xnor

The corresponding logic symbols for these gates are shown in figure. We consider gates with two inputs. These gates are instantiated to build logic circuits in Verilog. Examples of gate Instantiations are shown below. In the below example, for all instances, OUT is connected to the output out, and IN1 and IN2 are connected to the two inputs i1 and i2 of the gate primitives.

Gates symbol

The instance name does not need to be specified for primitives. More than two inputs can be specified in gate instantiation Gates with more two inputs are instantiated by simply adding more ports in the gate instantiation. Verilog automatically instantiates the appropriate gate.

Example Gate Instantiation of And/Or gates

The truth tables for these gates are given below, assuming two inputs. Outputs of gates with more than two inputs are computed by applying the truth table iteratively.

Buf/Bufif1/Bufif0/Not/Notfif1/Notfif0 Gates

Buf/not gates have one scalar input and one or more scalar output. The lasts terminal in the port list is connected to the input. Other terminals are connected the outputs.

Bufif1, Bufif0, Notif1, Notifo gates propagate only if their control signal is asserted. Such a situation is applicable when multiple drivers drive the signal.

These drivers are designed to drive the signal on mutually exclusive control. They propagate z if their control signal is deasserted.

buf not

bufif1 notfif1

bufif1 bufif0

Gates But, Not, Bufif1, Bufif0, Notif1, Notifo

Truth Table

Example Gate Instantiation of Buf/Not gates

From the above example, notice that theses gates can have multiple outputs but exactly one inputs, which is the last terminal in the port list.

The truth tables for these gates are shown below.

Examples

AND Gate from NAND Gate

Structural model of AND gate from two NANDS

module and_from_nand();

reg X, Y;

wire F, W;

// Two instantiations of the module NAND

nand U1(W,X, Y);

nand U2(F, W, W);