Every signal has a data type associated with it:
- Explicitly declared with a declaration in your Verilog code.
- Implicitly declared with no declaration when used to connect structural building blocks in your code. Implicit declaration is always a net type "wire" and is one bit wide.
Data Types Value set
Verilog supports four values and eight strengths to model the functionality of real hardware. The four levels are listed in table
Value level Condition in hardware circuits
0 logic zero, false condition
1 logic one, true condition
x unknown value
z High impedance, floating state
Nets
Nets represent connections between hardware elements. Just as in real circuits, nets have values continuously driven on them by the outputs of devices that they are connected to.
Types of Nets
| Net Data Type | Functionality |
| wire, tri | Interconnecting wire - no special resolution function |
| wor, trior | Wired outputs OR together (models ECL) |
| wand, triand | Wired outputs AND together (models open-collector) |
| tri0, tri1 | Net pulls-down or pulls-up when not driven |
| supply0, supply1 | Net has a constant logic 0 or logic 1 (supply strength) |
| Trireg | Retains last value, when driven by z (tristate) |
Register Data Types
- Registers store the last value assigned to them until another assignment statement changes their value.
- Registers represent data storage constructs.
- You can create regs arrays called memories.
- Register data types are used as variables in procedural blocks.
- A register data type is required if a signal is assigned a value within a procedural block
- Procedural blocks begin with keyword initial and always.
Example
| Data Types | Functionality |
| reg | Unsigned variable |
| integer | Signed variable - 32 bits |
| time | Unsigned integer - 64 bits |
| real | Double precision floating point variable |
Vectors
Nets or reg data types can be declared as vectors. If bit width is not specified, the default is scalar (1-bit).Vectors can be declared at [high#: low#] or [low#: high#], but the left number in the squared brackets is always the most significant bit of the vector.
Examples
wire a // scalar net variable default
wire [7:0]bus; // 8-bit bus
wire [31:0] busA, busB, busC; // 3 buses of 32-bit width
reg clock // scalar register
busA[7]; // bit #7 of vector busA
bus [2:0] // three least significant bits of vector bus
Integer, Real and Time Register Data Types
Integer
An integer is a general purpose register data type used for manipulating quantities. Integers are declared by the keyword integer. Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for purposes such as counting. The default width for an integer is the host-machine word size, which is implementation specific but is at least 32 bits. Registers declared as data type reg store values as unsigned quantities, whereas integers store value as signed quantities.
Example
integer counter; // general purpose variable used as a counter
initial
counter=-1; // A negative one is stored in the counter
Real
Real number constants and real register data types are declared with the keyword real. They can be specified in decimal notation (e.g., 5.12) or in scientific notation (e.g., 5e6, which is 5x10^6). Real numbers cannot have a range declaration, and their default value is 0. When a real value is assigned to an integer, the real number is rounded off to the nearest integer.
Example
real delta; // define a real variable called delta
initial
begin
delta=4e10; // delta is assigned in scientific notation
delta=2.13 ; // delta is assigned a value 2.13
end
integer i; // define an integer i
Time
Verilog simulation is done with respect to simulation time. A special time register data type is used in Verilog to store simulation time. A time variable is declared with the keyword time. The width for time register data types is implementation specific but is at least 64 bits. The system function $time is invoked to get the current simulation time.
Example
time save_sim_time; // define a time variable save_sim_time
initial
save_sim_time=$time; // save the current simulation time
Arrays
Arrays are allowed in Verilog for reg, integer, time and vector register data types. Arrays are not allowed for real variables. Arrays are accessed by
Example
integer count[7:0]; // an array of 8 count variables
reg bool[31:0]; // array of 32 one-bit Boolean register variables
integer matrix[4:0][4:0]; // illegal declaration Multidimensional array
Memories
In digital simulation, one often needs to model register files, RAMs and ROMs. Memories are modeled in Verilog simply as an array of registers. Each element of the array is known as a word. Each word can be one or more bits. It is important to differentiate between n 1-bit registers and one n-bit register. A particular word in memory is obtained by using the address as a memory array subscript.
Example
reg mem1bit[0:1023]; // memory mem1bit with 1K 1-bit words
reg [7:0]membyte[0:1023]; // memory membyte with 1K 8-bit words
Parameters
Verilog allows constants to be defined in a module by the keyword parameter. Parameters cannot be used as variables. Parameter values for each module instance can be overridden individually at compile time. This allows the module instances to be customized.
Example
parameter port_id = 5; //Defines a constant port_id
parameter cache_line_width= 256; // Constant defines width of cache line
Strings
Strings can be stored in reg. The width of the register variables must be large enough to hold the string. Each character in the string takes up 8 bits (1 byte). If the width of the register is greater than the size of the string, Verilog fills bits to left of the string with zeros. If the register width is smaller than the string width, Verilog truncates the leftmost bits of the string. It is always safe to declare that is slightly wider than necessary.
Example
reg [8*81:1] string_value; // declare a variable that is 18 bytes wide
initial
string_value=”hello Verilog course team”; // string can be stored in variable
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