Dataflow Modeling

Dataflow modeling:

In this style of modeling, the internal working of an entity can be implemented using concurrent signal assignment.
Let’s take half adder example which is having one XOR gate and a AND gate.

Library IEEE;

use IEEE.STD_LOGIC_1164.all;
entity ha_en is
port (A,B:in bit;S,C:out bit);
end ha_en;

architecture ha_ar of ha_en is
begin
S<=A xor B;
C<=A and B;
end ha_ar;

Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic type, called STD_ULOGIC. use is a keyword, which imports all the declarations from this package. The architecture body consists of concurrent signal assignments, which describes the functionality of the design. Whenever there is a change in RHS, the expression is evaluated and the value is assigned to LHS.