Structural Modeling

Structural modeling:

The implementation of an entity is done through set of interconnected components.
It contains:
• Signal declaration.
• Component instances
• Port maps.
• Wait statements.

Component declaration:

Syntax:
component component_name [is]
List_of_interface ports;
end component component_name;

Before instantiating the component it should be declared using component declaration as shown above. Component declaration declares the name of the entity and interface of a component.

Let’s try to understand this by taking the example of full adder using 2 half adder and 1 OR gate.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity fa_en is
port(A,B,Cin:in bit; SUM, CARRY:out bit);
end fa_en;


architecture fa_ar of fa_en is

component ha_en
port(A,B:in bit;S,C:out bit);

end component;


signal C1,C2,S1:bit;

begin

HA1:ha_en port map(A,B,S1,C1);
HA2:ha_en port map(S1,Cin,SUM,C2);
CARRY <= C1 or C2;

end fa_ar;

Publish Post

The program we have written for half adder in dataflow modeling is instantiated as shown above. ha_en is the name of the entity in dataflow modeling. C1, C2, S1 are the signals used for internal connections of the component which are declared using the keyword signal. Port map is used to connect different components as well as connect components to ports of the entity.

Component instantiation is done as follows.

Component_label: component_name port map (signal_list);

Signal_list is the architecture signals which we are connecting to component ports. This can be done in different ways. What we declared above is positional binding. One more type is the named binding. The above can be written as,

HA1:ha_en port map(A => A,B => B, S => S1 ,C => C1 );

HA2:ha_en port map(A => S1,B => Cin, S=> SUM, C => C2);