Programming in HDL: Switch Level Modeling

SWITCH LEVEL MODELING

Usually, transistor level modeling is referred to model in hardware structures using transistor models with analog input and output signal values. On the other hand, gate level modeling refers to modeling hard-ware structures wing gate models with digital input and output signal values between these two modeling schemes is referred to as switch level modeling. At this level, a hardware component is described

at the transistor level, but transistors only exhibit digital behavior and their input, and output signal values are only limited to digital values. At the switch level, transistors behave as on-off switches_- Verilog uses a 4 value logic value system, so Verilog switch input and output signals can take any of the four 0, 1, Z, and X logic values.

Switch level primitives

Table shows Verilog switch and pull primitives. Switches are unidirectional or bidirectional and resistive or nonresistive. For each group those primitives that switch on with a positive gate {like an NMOS transistor} and those that switch on with a negative gate {like a PMOS transistor}. Switching on means that logic values flow from input transistor to its input. Switching off means that the output of a transistor is at Z level regardless of its input value.A unidirectional transistor passes its input value to its output when it is switched on. A bidirectional transistor conducts both ways. A resistive structure reduces the strength of its input logic when passing it to its output. In addition to switch level primitives, pull-primitives that are used as pull-up and pull-down resistors for tri-state outputs.

Figure shows standard switches; pull primitives, and tri-state gates that behave like nmos and pmos. Instantiations of these primitives and their corresponding symbols are also shown. Cmos is a unidirectional transmission gate with a true and complemented control lines. Nmos and pmos are unidirectional pass gates representing NMOS and PMOS transistors respectively.

When such a resistive switch conducts, the strength of its output signal is one or two levels below that of its input signal. Delay values for transition to 1, transition to 0, and transition to Z can be specified in the #(to-1, to-0, to-z) format for unidirectional switches. Bidirectional tran switches shown in figure are functionally equivalent to unidirectional switches shown in the adjacent column of this figure. When conducting, the two inout ports are connected and logic values flow in both directions.

MOS switches

Two types of MOS switches can be defined with the keywords nmos and pmos. Keyword nmos is used to model NMOS transistors, Keyword pmos is used to model PMOS transistors. The symbols for nmos and pmos switches are shown in figure.

PMOS and NMOS Switches

In Verilog nmos and pmos switches are instantiated as shown in below,

nmos n1(out, data, control); // instantiate a nmos switch

pmos p1(out, data, control); // instantiate a pmos switch

Since switches are Verilog primitives, like logic gates, the name of the instance is optional. Therefore, it is acceptable to instantiate a switch without assigning an instance name.

nmos (out, data , control); // instantiate nmos switch ; no instance name

pmos (out, data, control); // instantiate pmos switch; no instance name

Value of the out signal is determined from the values of data and control signals. Logic tables for out are shown in table. Some combinations of data and control signals cause the gates to output to either a 1 or 0 or to an z value without a preference for either value. The symbol L stands for 0 or Z; H stands for 1 or z.

Logic Tables of NMOS and PMOS

Thus, the nmos switch conducts when its control signal is 1. If control signal is 0, the output assumes a high impedance value. Similarly a pmos switch conducts if the control signal is 0.

CMOS Switches

CMOS switches are declared with the keyword cmos. A cmos device can be modeled with a nmos and a pmos device. The symbol for a cmos switch is shown in figure

CMOS switch

A CMOS switch is instantiated as shown in below,

cmos cl(out, data, ncontrol, pcontrol);//instantiate cmos gate

cmos (out, data, ncontrol, pcontrol); //no instance name given

The ncontrol and pcontrol are normally complements of each other. When the ncontrol signal is 1 and pcontrol signal is 0, the switch conducts. If ncontrol is 0 and pcontrol is

1, the output of the switch is high impedance value. The cmos gate is essentially a combination of two gates: one nmos and one pmos. Thus the cmos instantiation shown above is equivalent to the following.

nmos (out, data, ncontrol); //instantiate a nmos switch

pmos (out, data, pcontrol); //instantiate a pmos switch

Since a cmos switch is derived from nmos and pmos switches, it is possible derive the output value from Table, given values of data, ncontrol, and pcontrol signals.

Bidirectional Switches

NMOS, PMOS and CMOS gates conduct from drain to source. It is important to have devices that conduct in both directions. In such cases, signals on either side of the device can be the driver signal. Bidirectional switches are provided for this purpose. Three keywords are used to define bidirectional switches: tran, tranif0, and tranifl.

Symbols for these switches are shown in figure below.

Bidirectional switches

The tran switch acts as a buffer between the two signals inoutl and inout2. Either inoutl or inout2 can be the driver signal. The tranif0 switch connects the two signals inoutl and inout2 only if the control signal is logical 0. If the control signal is a logical 1, the nondriver signal gets a high impedance value z. The driver signal retains value from its driver. The tranifl switch conducts if the control signal is a logical 1.

These switches are instantiated as shown in below

tran tl(inoutl, inout2); //instance name tl is optional

tranifO (inoutl, inout2, control); //instance name is not specified

· Resistive switches reduce signal strengths when signals pass through them. The changes are shown below. Regular switches retain strength levels of signals from input to output. The exception is that if the input is of supply, the output is of strength strong. Below table shows the strength reduction due to resistive switches

Input strength Output strength

supply pull

strong pull

pull weak

weak medium

large medium

medium small

small small

high high

Strength reduction by resistive switches

Delay Specification on Switches

MOS and CMOS switches

Delays can be specified for signals that pass through these switch-level elements. optional and appear immediately after the keyword for the switch.

Switch element

Delay specification

Examples

Pmos,nmos,rpmos,rnmos

Zero (no delay)

One (same delay on all transitions)

Two (rise,fall)

Three (rise,fall,turnoff)

pmos p1(out,data,control);

pmos#(1)

p1(out,data,control);

nmos #(1,2) p2(out,data,control);

nmos #(1,3,2) p2(out,data,control);

Cmos,rcmos

Zero, one,two or three delays (same as above)

cmos #(5) c2(out,data,nctrl,pctrl);

cmos #(1,2) c1(out,data,nctrl,pctrl);

Delay Specification on NMOS and CMOS switches

Bidirectional pass switches

Delay specification is interpreted slightly differently for bidirectional pass switches. These switches do not delay signals passing through them. Instead, they have turn-on and turn-off delays while switching. Zero, one, or two delays can b specified for bidirectional switches, as shown in Table.

Switch element

Delay specification

Examples

tran, rtran

No delay specification allowed

tranif1,rtranif1

tranif0,rtranif0

Zero (no delay)

One (both turn-on and turn-off)

Two (turn-on, turn-off)

rtranif0 rt1(inout1,inout2,control);

tranif0#(3) T(inout1,inout2,control);