Lexical Conventions
The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings, identifiers, and keywords. Verilog HDL is a case-sensitive language. All keywords are in lower case.
Whitespace
White space can contain the characters for blanks, tabs, newlines, and form feeds. These characters are ignored except when they serve to separate other tokens. However, blanks and tabs are significant in strings.
White space characters are:
- Blank spaces (\b)
- Tabs(\t)
- Carriage returns(\r)
- New-line (\n)
- Form-feeds (\a)
Example
Comments
Comments can be inserted in the code for readability and documentation. There are two forms to introduce comments.
- Single line comments begin with the token // and end with a carriage return
- Multi line comments begin with the token /* and end with the token */
Example
Identifiers and Keywords Identifiers are names used to give an object, such as a register or a function or a module, a name so that it can be referenced from other places in a description. Keywords are reserved to define the language constructs.
- Identifiers must begin with an alphabetic character or the underscore character (a-z A-Z _ )
- Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ )
- Identifiers can be up to 1024 characters long.
- Keywords are in lowercase.
- data_input mu
- clk_input my$clk
- i386
Examples of keywords
- always
- begin
- end
- Escaped identifiers begin with the back slash ( \ )
- Entire identifier is escaped by the back slash.
- Escaped identifier is terminated by white space (Characters such as commas, parentheses, and semicolons become part of the escaped identifier unless preceded by a white space)
- Terminate escaped identifiers with white space, otherwise characters that should follow the identifier are considered as part of it.
Numbers in Verilog
Integer Numbers
Verilog HDL allows integer numbers can be specified as
- Sized or unsized numbers (Unsized size is 32 bits)
- In a radix of binary, octal, decimal, or hexadecimal
- Radix and hex digits (a,b,c,d,e,f) are case insensitive
- Spaces are allowed between the size, radix and value
Integer numbers are represented as
12’habc – this is a 12-bit hexadecimal number
16’d255 – this is a 16-bit decimal number
8’o44-this is 8 bit octal number
- Verilog supports real constants and variables
- Verilog converts real numbers to integers by rounding
- Real Numbers can not contain 'Z' and 'X'
- Real numbers may be specified in either decimal or scientific notation
- <>.<>
- <>E<>
- Real numbers are rounded off to the nearest integer when assigning to an integer.
Example
Real Number | Decimal notation |
| 1.2 | 1.2 |
| 0.6 | 0.6 |
| 3.5E6 | 3,500000.0 |
Signed and Unsigned Numbers
Verilog supports both types of numbers, but with certain restrictions. Like in C language Verilog don't have int and unint types to say if a number is signed integer or unsigned integer. Any number that does not have negative sign prefix is a positive number. Or indirect way would be "Unsigned".
Negative numbers can be specified by putting a minus sign before the size for a constant number, thus they become signed numbers. Verilog internally represents negative numbers in 2's complement format. An optional signed specifier can be added for signed arithmetic.
Example
| Number | Description |
| 32'hDEAD_BEEF | Unsigned or signed positive number |
| -14'h1234 | Signed negative number |
Example
module signed_number;
reg [31:0] a;
initial begin
a = 14'h1234;
$display ("Current Value of a = ‰h", a);
a = -14'h1234;
$display ("Current Value of a = ‰h", a);
a = 32'hDEAD_BEEF;
$display ("Current Value of a = ‰h", a);
a = -32'hDEAD_BEEF;
$display ("Current Value of a = ‰h", a);
#10 $finish;
end
endmodule
Strings
A string is a sequence of characters that are enclosed by double quotes. The restriction on a string is that it must be contained on a single line, that is, without a carriage return. It cannot be on multiple lines, Strings are treated as a sequence of one-byte ASCII values.
Examples
“hello Verilog world”
“a/b”
“aa+a”
Verilog Course Team is EDS for VLSI is being managed by Engineers/Professionals possesing significant industrial experience across various application domains and engineering horizontals.Our engineers have expertise across a wide range of technologies,to the engineering efforts of our clients.Leveraging standards based components and investments in dedicated test lab infrastructure,we offer innovative,flexible and cost-effective Services and Solutions.