Modeling a Test Bench

Test bench:

Once a design block is completed it must be tested. The functionality of the design block can be tested by applying stimulus and checking the result. We call such a block the Stimulus block. It is good practice to keep the stimulus and design blocks separate. The stimulus block can be written in VHDL. A separate language is not required to describe the stimulus. The stimulus block is also commonly called a Test Bench

The test bench is used for generating stimulus for the entity under test. Let’s write a simple test bench for full adder.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity tb_en is

end tb_en;

architecture tb_ar of tb_en is

signal a_i,b_i,c_i,sum_i,carry_i:bit;

begin

eut: entity work.fa_en(fa_ar)

port map(A=>a_i,B=>b_i,Cin=>c_i,SUM=>sum_i,CARRY=>carry_i);

stimulus: process

begin

a_i<='1';b_i<='1';c_i<='1';

wait for 10ns;

a_i<='0';b_i<='1';c_i<='1';

wait for 10ns;

a_i<='1';b_i<='0';c_i<='0';

wait for 10ns;

if now=30ns then

wait;

end if;

end process stimulus;

end tb_ar;

Here now is a predefined function that returns the current simulation time.

What we saw upto this is component instantiation by positional and by name. In this test bench example the entity is directly instantiated. The direct entity instantiation syntax is:

Component_label: entity entity_name (architecture_name)
port map(signal_list);