In real circuits, logic gates have delays associated with them. Gate delays allow the Verilog user to specify delays through the logic circuits. Pin-to-pin delays can also be specified in Verilog.
Rise, Fall, and Turn-off Delays
There are three types of delays from the inputs to the output of a primitive gate
Rise delay
The rise delay is associated with a gate output transition to a 1 from another value.
Fall delay
Turn-off delay
If the value changes to X, the minimum of the three delays is considered.
Example for Delay Specification
Min/Typ/Max Values
Verilog provides an additional level of control for each type of delay mentioned. For each type of delay-rise, fall, and turn-off-three values, min, typ and, max can be specified. Any one value can be chosen at the start of the simulation. Min/ typ /max values are use to model devices whose delays vary within a minimum and maximum range because of the IC fabrication process variations.
Min value
The min value is the minimum delay value that the designer expects the gate to have.
Typ value
The typ value is the typical delay value that the designer expects the gate to have.
Max value
The max value is the maximum delay value that the designer expects the gate to have.
Min, typ, or max values can he chosen at Verilog run time. Method of choosing a min/typ/max value may vary for different simulators or operating systems. (For Verilog-XLTM, the values are chosen by specifying options +maxdelay, +typdelay, and +mindelays at run time. If no option is specified, the typical delay value is the default). This allows the designers the flexibility of building three delay values for each transition into their design. The designer can experiment with delay values without modifying the design.
Examples of Min, Max and Typical Delay Values
Timing controls
Various behavioral timing control constructs are available in Verilog. In Verilog, if there are no timing control statements, the simulation time does not advance. Timing controls provide a way to specify the simulation time at which procedural statements will execute.
There are three methods of timing control:
- Delay based timing control
- Event based timing control
- Level-sensitive timing control
Delay-based timing control
Delay-based timing control in an expression specifies the time duration between when the statement is encountered and when it is executed. Delays are specified by the symbol #. Syntax for the delay-based timing control statement is shown below
::= #
||= #
||= #
Delay-based timing control can be specified by a number, identifier, or a mintypmax_expression. There are three types of delay control for procedural assignments
- Regular delay control
- Intra-assignment delay control
- Zero delay control
Regular delay control
Regular delay control is used when a non-zero delay is specified to the left of a procedural assignment. Usage of regular delay control is shown below example,
module clk_gen ();reg clk, reset; initial begin $monitor ("TIME = %g RESET = %b CLOCK = %b", $time, reset, clk); clk = 0; reset = 0; #2 reset = 1; #5 reset = 0; #10 $finish;end always #1 clk = !clk; endmodule Intra-assignment delay control
Instead of specifying delay control to the left of the assignment, it is possible to assign a delay to the right of the assignment operator. Usage of intra-assignment delay control is shown in below example,
module intra_assign();reg a, b; initial begin $monitor("TIME = %g A = %b B = %b",$time, a , b); a = 1; b = 0; a = #10 0; b = a; #20 $display("TIME = %g A = %b B = %b",$time, a , b); $finish;end endmoduleDifference between the intra-assignment delay and regular delay
Regular delays defer the execution of the entire assignment. Intra-assignment delays compute the right-hand-side expression at the current time and defer the assignment of the computed value to the left-hand-side variable. Intra-assignment delays are like using regular delays with a temporary variable to store the current value of a right-hand-side expression.
Zero delay control
Zero delay control is a method to ensure that a statement is executed last, after all other statements in that simulation in that simulation time are executed. This is used to eliminate race conditions. However, if there are multiple zero delay statements, the order between them is nondeterministic. Usage of zero delay control is shown in below example,
initial
begin
x=0;
y=0;
end
initial
begin
#0 x=1;
#0 y=1;
End
Above four statements x=0,y=0,x=1,y=1 are to be executed at simulation time 0. However since x=1 and y=1 have #0, they will be executed last. Thus, at the end of time 0,x will have value 1 and y will have value 1.
Event based timing control
An event is the change in the value on a register or a net. Events can be utilized to trigger execution of a statement or a block of statements. There are four types of event-based timing control
- Regular event control
- Named event control
- Event OR control
- Level-sensitive timing control
Regular event control
The @ symbol is used to specify an event control. Statements can be executed on changes in signal value or at a positive or negative transition of the signal value. The keyword posedge is used for a negative transition as shown in below example,
module edge_wait_example();reg enable, clk, trigger; always @ (posedge enable)begin trigger = 0; // Wait for 5 clock cycles repeat (5) begin @ (posedge clk) ; end trigger = 1; end Named event control
Verilog provides the capability to declare an event and then trigger and recognize the occurrence of that event. The event does not hold any data. A named event is declared by the keyword event. An event is triggered by the symbolà. The triggering of the event is recognized by the symbol @.
Example
event received_data;
always @(posedge clock)
begin
if (last_data_packet)
àreceived_data;
end
always @(received_data)
data_buf={data_pkt[0],data_pkt[1]};
Event OR control
Sometimes a transition on any one of multiple signals or events can trigger the execution of a statement or a block of statements. This is expressed as an OR of events or signals. The list of events or signals expressed as an OR is also known as a sensitivity list. The keyword or is used to specify multiple triggers as shown in below example,
always @(reset or clock or d)
begin
if(reset)
q=1’b0;
else if (clock)
q=d;
end
Level-Sensitive Timing Control
Verilog allows a level-sensitive timing control, that is, the ability to wait for a certain condition to be true before a statement or a block of statements is executed. The keyword wait is used for level-sensitive constructs.
Example
always
wait (count_enable) #20 count=count+1;
From the above example, the value of count_enable is monitored continuously. If count_enable is 0, the statement is not entered. If it is logical 1, the statement count=count+1 is executed after 20 time units. If count_enable stays at 1, count will be incremented every 20 time units.
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